1. Field of the Invention
The present invention pertains to cache memories. More particularly, this invention relates to a write combining buffer that supports snoop requests.
2. Background
As the use of and need for computer systems has increased, so too has the desire for ever-increasing performance. Faster and faster processors and computer systems are continually being developed to meet the needs of users throughout the world. One feature commonly found in processors to increase their performance is one or more cache memories. A cache memory is a memory unit that is smaller than the system memory (or the next higher level cache memory), but that operates at a faster speed than the system memory (or the next higher level cache memory). The goal of the cache memory is to contain the information (whether it be data or operations) that the execution unit(s) of the processor is going to use next. This information can then be returned to the execution unit(s) much more quickly, due to the higher speed of the cache memory.
Two types of cache memories are commonly used, one being referred to as a xe2x80x9cwritebackxe2x80x9d cache, while the other is referred to as a xe2x80x9cwritethroughxe2x80x9d cache. The writeback cache can contain a different version of data (e.g., a modified version) than is contained in the higher level cache memory or system memory. When necessary, modified data from the cache is written back to the higher level cache memory or system memory. The writethrough cache does not contain different versions of data than the higher level cache memory or system memory. Rather, when modified data is written to the cache, it is also written xe2x80x9cthroughxe2x80x9d the cache to the higher level cache memory or system memory, thereby avoiding any need to writeback data.
However, one problem that exists with writethroug cache memories is the traffic that occurs on the bus between the memories. Because each of the writes is passed through the first cache memory to the second cache memory, a large amount of data is transferred between the two memories. One solution to this data traffic problem is to use a write combining buffer to temporarily store write data from the first cache memory to the second cache memory. However, in a multiprocessor environment that needs to support accesses from multiple processors, this is not straightforward to do. Multithreaded processors further complicate implementation of write combining buffers. One option is to support only weak-ordered memory (e.g., non-speculative, non-snooped memory types), thereby eliminating the need to be concerned with cache coherency. However, given the amount of speculative and snooped memory types that are used in current processors, such a constraint greatly limits the situations in which the write combining buffer can be used. There is currently no way to provide support for such a write combining buffer for other than weak-ordered memory. The present invention provides such support.
A write combining buffer that supports snoop requests is described herein. According to one aspect of the present invention, an apparatus includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store operations. Each of the plurality of store operations is to at least a part of a cache line, and the write combining buffer can be snooped in response to requests initiated external to the apparatus. In multithreaded embodiments, snoops can be in response to other threads.
According to one aspect of the present invention, a method includes receiving a plurality of store operations to a cache line and temporarily storing data corresponding to the plurality of store operations in a write combining buffer of an apparatus. The method also includes snooping the write combining buffer in response to requests initiated external to the apparatus. In multithreaded embodiments, snoops can be in response to other threads.